This invention pertains to the matched filtering of high speed digital data. Generally, noisy data, which is in analogue form, is required to be decoded into digital ones or zeros. The digital data matched filtering process is one of integrating an input signal over a known bit time and determining at the end of the integration whether the result is positive or negative. Theoretically, this provides optimal detection by maximizing the signal-to-noise ratio, since over the entire bit time, the effects of noise tend to cancel out. Integration is typically performed in analogue form by charging a capacitor, which must then be dumped prior to starting a new integration. In high speed data systems, this dumping process can take a significant time with respect to a bit time. The result is less integration time, and consequentially, sub-optimal detection. Split-phase matched filters allow one phase to be integrating while the alternate phase is dumping. This provides a full bit time to integrate the signal, while simultaneously providing a full bit time to dump the charge on the capacitor. The standard approach for this technique is to use two independent comparators, then logically selecting the active one.
The prior art split-phase matched filter mentioned above requires two independent comparators because only the positive input of each comparator is used. Because comparators are generally higher in power and more expensive than logic elements, the need for a new split-phase matched filter has arisen.